Integrated circuits include conductive layers separated by dielectric layers overlaying a semiconductive substrate. It is necessary to provide selected electrical contact from an upper metallic layer to one or more of the conductive layers and regions in the substrate. If proper electrical contact from the metallic layers is not made, the integrated circuit will fail. It is therefore critical to ensure that electrical contact is properly made.
A common technique to make electrical contact to the substrate (or a conductive layer) is to form a hole in the dielectric layer or layers over the substrate, exposing a region in the substrate. A metallic layer is then deposited on the dielectric layer, filling the hole and extending to the substrate to make the electrical contact. This technique provides acceptable electrical contact to the substrate if the hole is sufficiently large in diameter. If the hole width dimensions are too small , the conductive layer will not reach the substrate and electrical contact is not formed between the layers and the substrate. In LSI and VLSI fabrication processes, geometrics and linewidths of 1 .mu.m or less are used. The formation of electrical contacts with the semiconducting substrate and of the interconnection vias from an upper metallic layer is very difficult because of the extremely small sizes of the contract holes, which they must necessarily assume at such small features.